Md Kamrul Islam — Design Verification Engineer, MEngSc student at University College Cork
Turning complex IP into verified silicon.
I'm also a HARDWARE RELIABILITY ENTHUSIAST.
Design verification engineer with 4.5 years' industry experience verifying complex IP across RTL and gate-level domains, from Trainee to Senior Engineer at ULKASEMI. Delivered verification of DDR PHY, USB Power Delivery controller and RTC IP, with 80+ silicon-critical bugs found and >95% coverage closure. Now pursuing an MEngSc in Electrical & Electronic Engineering at University College Cork, deepening my knowledge of digital, analogue and mixed-signal IC design.
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Engineer, researcher, and silicon problem hunter.
Hello! I'm Md Kamrul Islam, a design verification engineer and, since September 2026, an MEngSc student in Electrical & Electronic Engineering at University College Cork. For four and a half years at ULKASEMI Pvt. Limited I worked where RTL intent meets real sign-off pressure: UVM testbenches, gate-level simulation, coverage closure, waveform debug, and automation.
My work combined verification planning, reusable UVM methodology, GLS debug, client communication, and mentoring junior engineers. My research interests: Variation-aware low-power digital VLSI and circuit design; circuit–architecture co-design for AI and neuromorphic accelerators; secure and reliable SoC/IoT architectures; ASIC/SoC design verification and hardware security.
I'm currently in Cork completing an MEngSc at UCC. My General Co-op Placement at Analog Devices (ADI), Cork, is confirmed for – as part of my MEngSc in Electrical & Electronic Engineering. I remain interested in research collaborations in digital design, verification and low-power VLSI. A PhD is my longer-term goal.
Electronic Engineering
10 May – 24 Sep 2027
Academic Background
Research & Publications
Research interests at the intersection of hardware reliability, intelligent systems, and secure SoC architecture.
Projects with measurable outcomes.
Gate-level sign-off readiness of DDR PHY IP through multi-corner GLS regressions, X-propagation debug, UVM updates, and power-analysis support.
- Identified/resolved 30+ tape-out critical functional issues across multiple DDR PHY products
- Reduced GLS debug cycles by ~30% via automation
- Led a team of 1 engineer and 2 assistant engineers; ran weekly client meetings to hit tape-out milestones
Refactored RTL-provided linear testbench, automated GLS execution, and debugged X-propagation failures to stabilise regressions.
- Improved GLS readiness and regression stability
- Enabled repeatable GLS execution with lower manual effort
End-to-end verification sign-off of RTC IP with reusable UVMF-style UVM environment, RAL model, coverage model, assertions, and waiver tracking.
- Achieved ~98% functional and code coverage
- Caught 25+ functional bugs
- Reduced verification time by ~30% using Bash automation
Verified USB-PD controller subsystems across RTL and GLS through constrained-random tests, global assertions, coverage models, and regression triage.
- Found 25+ pre-silicon functional bugs
- Developed 80+ constrained-random testcases for state machines and timing paths
- Contributed to first-silicon success
Built multi-agent UVM testbench for Wishbone-I2C and APB-SPI, and single-agent for APB/AHB; authored test/coverage plans and automation scripts.
- Achieved >90% functional coverage
- Cut test cycle time ~30% with Bash/Python automation
Built a rooftop PV/weather data acquisition setup and ANN/MLP workflow to analyse clean vs. dusty PV module behaviour under real environmental conditions.
- Published 3 IEEE conference papers
- Found temperature as most correlated parameter with PV output
Professional Journey
General Co-op Placement
- Work placement as part of the MEngSc in Electrical & Electronic Engineering at University College Cork.
Senior Engineer, Design Verification
- Progressed Trainee Engineer (Feb 2022) → Assistant Engineer (May 2022) → Engineer (Jan 2024) → Senior Engineer, Design Verification (Jan 2025 — Aug 2026).
- Contracted to a tier-1 EDA vendor, verifying gate-level netlists of DDR PHY hard IP.
- Verified a USB Power Delivery controller IP for a major semiconductor client.
- Owned verification plans, DV strategy and sign-off for blocks/subsystems; architected UVM testbenches and drove coverage closure with justified waivers.
- Ran regressions and GLS, debugging protocol, timing and corner-case issues — including low-power, reset and clocking scenarios — and drove root-cause fixes with design.
- Led and mentored engineers on client projects: recruitment, training, task allocation, work reviews, performance appraisals and weekly client status meetings.
Software Engineer Intern
- Developed cross-platform mobile applications using Flutter for Android and iOS.
- Implemented UI/UX designs into functional app screens, managed state, and integrated REST APIs.
- Collaborated in an agile team environment from initial design through deployment on app stores.
Student Tutor — EEE301
- Conducted topic sessions based on students' needs; assisted faculty with assessments.
- Helped weaker students overcome difficulties in specific topics.
Technical Expertise
Training & Certifications
Get in Touch
General Co-op Placement confirmed at Analog Devices (ADI), Cork, for 10 May – 24 September 2027. Get in touch about research collaborations, verification, or low-power VLSI.
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